The present invention relates to the testing of integrated circuits and, more specifically, to a versatile built-in self-test that provides both on-line and off-line integrated circuit testing.
Conventional integrated circuits (such as microprocessors and digital signal processors) typically are defined as a collection of interconnected basic functional units. The functional units define operations that are repeatedly used in a given design. For example, a storage register functional unit defines a circuit that stores a data word in the integrated circuit. Arithmetic functional units such as adders define circuits that add two data words in the integrated circuit. An integrated circuit, then, consists of a particular collection of registers, adders, etc., that are connected in such a manner as to provide the overall functionality defined for the integrated circuit. In practice, integrated circuits typically contain thousands of functional units such as those described above.
A variety of testing schemes have been used to ensure that an integrated circuit performs as intended. For example, the built-in self-test (xe2x80x9cBISTxe2x80x9d) scheme tests the functional units of an integrated circuit using additional circuitry that is built into the integrated circuit. BIST techniques have been used in both off-line and on-line integrated circuit testing.
Off-line BIST is used to test the integrated circuit while the integrated circuit is not in use. For example, off-line BIST typically is used to test integrated circuit devices during production.
In off-line BIST, the test circuitry generates test patterns and compacts the responses the functional units of the integrated circuit had to the test patterns. Typical BIST structures used for off-line testing include linear feedback shift register (LFSR) pattern generators for generating the test patterns and multiple input signature register (MISR) test response compactors for compressing the test responses. Conventionally, these test structures are only used during a test mode.
Off-line BIST schemes have been used to test data-path architectures in digital signal processors. Regular structures such as multipliers, adders, subtractors, registers, and arithmetic logic units form the core of these architectures. Research has shown that these regular structures are testable using small, constant size test sets (C-testable). See, for example, the paper entitled xe2x80x9cAn Effective BIST Scheme for Data Pathsxe2x80x9d by Gizopoulos, D., et al., Proc. International Test Conference, pp. 76-85, November 1996. The fixed size of these test sets translates into a constant test application time. Research has also identified C-testable test sets that can be generated using regular blocks such as counters and accumulators.
On-line BIST is used to test the integrated circuit while the integrated circuit is in use. For example, on-line BIST may be used to test a microprocessor when the microprocessor is executing instructions. On-line BIST is primarily based on space, time or information redundancy. As a result, typical on-line BIST structures include replicated hardware, comparators and checkers.
Due in large part to the above described differences between on-line and off-line BIST structures, it may be relatively inefficient to implement both off-line and on-line BIST on the same integrated circuit. Studies have shown that such an implementation may require as much as 50% area overhead in comparison to a design without BIST. See, for example, Stroud, C., et al., xe2x80x9cA Parameterized VHDL Library For On-line Testing,xe2x80x9d Proc. International Test Conference, pp. 479-488, November 1997.
A variety of techniques have been proposed to improve testability of data-path designs. Controllability and observability have been used to guide testable data-path synthesis. Chen, C-H., et al., xe2x80x9cBETA: Behavioral Testability Analysis,xe2x80x9d Proc. International Conference on CAD, pp. 202-205, October 1991. Other testability metrics used in literature include the sequential depth, feedback loops and register adjacency. See, for example, T-C. Lee et al., xe2x80x9cBehavioral Synthesis for Easy Testability in Data Path Scheduling,xe2x80x9d Proc. IEEE International Conference on CAD, pp. 616-619, November 1992; S. Dey et al., xe2x80x9cSynthesizing Designs with Low-Cardinality MVFS for Partial Scan Synthesis,xe2x80x9d Proc. IEEE VLSI Test Symposium, pp. 2-7, April 1994; and, L. Avra et al., xe2x80x9cAllocation and Assignment in High-Level Synthesis for Self-Testable Data-Paths,xe2x80x9d Proc. International Test Conference,xe2x80x9d pp. 272-279, October 1992, respectively. To provide pseudo-random test patterns and to compact test responses, techniques have been developed to identify registers that can be transformed into LFSRs and MISRs. See S. Chiu and C. A. Papachristou, xe2x80x9cA Design for Testability Scheme with Applications to Data Path Analysis,xe2x80x9d Proc. IEEE/ACM Design Automation Conference, pp. 271-277, June 1991. The main objective of these techniques is to minimize the number of transformed registers. A proposed pseudo-exhaustive BIST scheme called arithmetic BIST ensures complete state coverage at the input of all functional units incorporated in the design. N. Mukherjee, J. Rajski, J. Tyszer, xe2x80x9cDesign of Testable Multipliers for Fixed-Width Data Paths.xe2x80x9d IEEE Trans. on Computers, vol. 46, no. 7, pp. 795-810, July 1997. A data-path BIST scheme has been proposed that (i) guarantees high fault coverage without time consuming iterative fault simulation; (ii) has an implementation independent fault model; and (iii) uses a small test set that is independent of the data-path width. See the Gizopoulos et al. paper referenced above. All these schemes are targeted toward off-line testing.
An article by R. Singh and J. Knight entitled xe2x80x9cConcurrent Testing in High-Level Synthesisxe2x80x9d, Proceedings of International Symposium on High-Level Synthesis, May 1994, pp. 96-103, discusses a pseudo-random testing method. The method involves 1) initially scheduling and allocating the functional data-flow graph; 2) determining a test data-flow graph by identifying test paths that will provide access to the functional units during their idle time; and 3) using LFSR for test pattern generation and MISR for test response compaction during the test phase. Here, internal registers of the circuit are converted into LFSRs and MISRs. In addition the method uses a separate BIST controller.
This method has several drawbacks. For example, the method typically will have a long test latency due to the use of the pseudo-random based test. This is because a large number of test patterns may be required to detect random-pattern resistant faults. This long test latency results, in turn, in relatively long test application times. In addition, this method typically requires a relatively high area overhead because a large number of registers are converted into LFSRs and MISRs, or because extra generators and compactors may be required.
A technique referred to as concurrent testing proposes a method of exploiting off-line testing resources for on-line testing. In concurrent testing, off-line testing resources are modified to observe the normal inputs and outputs of a combinational circuit under test during normal system operation. When a normal input matches a test pattern from its test set, the corresponding circuit output is compressed into a signature. K. K. Saluja, R. Sharma and C. R. Kime, xe2x80x9cA Concurrent Testing Technique for Digital Circuits,xe2x80x9d IEEE Trans. on Computer Aided Design, vol. 7, no. 12, pp. 1250-1260, December 1988.
Conventional integrated circuit testing techniques such as those described above may use a significant portion of the physical area of the device or they may not provide thorough testing in an efficient manner. As a result, a need exists for a more efficient and effective method of testing integrated circuits and related devices.
The invention provides a versatile BIST technique that provides both off-line and on-line integrated circuit testing using common test circuitry. Unlike traditional on-line BIST, a test according to the invention does not need to use functional data as test inputs. Rather, the test generates test patterns, applies test patterns and compacts test responses to test an integrated circuit in a manner similar to that employed by off-line BIST.
Significantly, the test functions are performed by the functional units of the original design (i.e., the design without BIST circuitry) in conjunction with additional functional resources comparable to those required by off-line BIST alone. According to the invention, an original design is modified so that the functional units of the original design perform test operations during idle processing cycles in the normal mode of operation.
Idle processing cycles exist during the operations of many integrated circuits. For example, integrated circuit operations can be implemented using basic functional units such as multipliers, adders and subtractors. In general, these functional units are not active in every clock cycle. In fact, there typically are only a few clock cycles (if any at all) in which all functional units are active simultaneously.
The functional units of the design are constrained to perform the test function by coordinating the generation and application of the test patterns and the compaction of the test responses with the usage profile of the functional units. In one embodiment, constraints to coordinate the test functions with the functional units are incorporated in Behavioral Compiler-generated arithmetic data-paths using Synopsys synthesis scripts. Following the allocation and scheduling phases of behavioral synthesis, an idleness profile of the design is generated. That is, the designer identifies idle computation cycles (defined as operators, e.g., adders or multipliers, and the clock cycles in which they are idle) in the basic design. Next, the test function is scheduled such that the operations in the test function only use the spare computation capacity in the design. The operations of the test function are then bound to the operators in the design so that all modules in the design are tested.
By coordinating test functions with the basic design functions and by using a small test set, a test procedure according to the invention can operate concurrently with the normal function, guarantee a very high fault coverage and perform the test in a relatively short period of time (e.g., on the order of a few milliseconds). As a result, the invention may effectively be used to test an integrated circuit during on-line operations.
In summary, the invention provides a versatile BIST technique that may be used both in an off-line production test mode and in an on-line field test mode. This is accomplished with minimal impact on the performance and physical area of the design in comparison to the impact made on the performance and area of a design by an off-line BIST scheme alone.